Pay Range: $89.11hr - $94.06hr

Job Overview:

In this role, the successful candidate will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. The candidate will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.

Candidate Profile:

The successful candidate is passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies. The candidate enjoys solving challenging problems, is detail-oriented, and thrives in a collaborative team environment, demonstrating enthusiasm for working with vibrant teams located across different time zones. With strong analytical skills and a methodical approach, the candidate is eager to learn, share knowledge, and contribute to building cutting-edge silicon.

Key Responsibilities:

- Develop and implement power reduction strategies across SoC/IP design.
- Perform synthesis and static timing analysis (STA) to achieve PPA targets.
- Analyze and optimize agile and leakage power using industry-standard tools.
- Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
- Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.




- Support sign-off activities for Lint, CDC, synthesis, timing, and power closure.
- Automate and streamline power and timing workflows to improve efficiency.
- Build test plan documentation, accounting for interactions with other features and the hardware.

Preferred Experience:

- Strong background in ASIC synthesis and static timing analysis (STA).
- Hands-on expertise with EDA tools such as Client Design Compiler, PrimeTime, PrimePower, Power Artists, or equivalent.
- Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).
- Familiarity with UPF/CPF power intent specification and verification.
- Solid understanding of digital design fundamentals and RTL coding (Verilog/SystemVerilog).
- Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm) is a strong plus.
- Proficiency in scripting languages (TCL, Perl, Python, or Shell) for flow automation.
- Exposure to floorplanning, place-and-route, and ECO flows is desirable.
- Knowledge of low-power design methodologies and trade-offs.
- Prior leadership, mentorship, or cross-functional collaboration experience is an asset.
- Experience with Verilog, SystemVerilog, C, and C++.
- Graphics pipeline knowledge.
- Experience automating workflows in a distributed compute environment.

📌 Senior ASIC RTL Design Engineer (Markham)
🏢 Cynet Systems
📍 Markham