What you'll do:
Develop mixed-signal PLL integrated circuits.
Create test benches and write test cases.
Contribute to ongoing digital verification projects.
What they're looking for:
Students in positive academic standing.
Proficiency in object-oriented programming.
Knowledge of Verilog, SystemVerilog, UVM, Python, or Tcl.
Solid English communication and problem-solving skills.
Pay and perks:
Hourly pay between $24 and $26 CAD.
Eligibility for quarterly innovation bonuses.
Includes equity grant opportunities.
J-18808-Ljbffr
📌 Asic Digital Verification Engineer Co Op Ottawa (Canada)
🏢 SiTime
📍 Canada
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