Collaborating with cross-functional teams, the full time Mask Design Engineer will design and develop detailed layouts of silicon interposers for NVIDIA products while addressing manufacturing and electrical design challenges in a hybrid work environment.
Key responsibilities Collaborate with package technical leads and design teams to deliver solutions for product packages on a tight schedule Perform physical layout for silicon interposers using Cadence tools and conduct design feasibility studies Propose layout design trade-offs and verify layouts against design rules and netlists Required qualifications B.S. in Electrical Engineering or equivalent experience 3+ years of proven experience in Mask and Layout Design Deep understanding of layout concepts in submicron CMOS technologies Proficiency with Cadence layout tools, particularly Virtuoso Experience with verification tools such as Calibre, ICV, and scripting languages like Perl or Python