Develop ASIC IP with Qualcomm Canada’s Soft IP team in Ottawa, using Verilog, SystemVerilog, and UVM during a four-month co-op.

This engineering co-op supports design and verification for standards-compliant IP blocks and subsystems. You will work with experienced engineers across Ethernet, UALink, UEC, ESUN, CXL, and PCIe FPGA or ASIC projects. The assignment offers hands-on exposure to hardware design and verification techniques.

Key Responsibilities:
Develop and document verification settings using SystemVerilog and UVM
Develop and document designs using Verilog
Execute individual RTL test cases
Track bug reports from inception through closure
Develop scripts supporting the development process

Requirements:
Complete second-year bachelor's or master's studies in a related field
Available for four months from January 2027 through April or May
Experience with Python, Perl, TCL, and Unix/Linux shell scripting
Experience with source code revisioning systems
Expected graduation date of November 2027 or later

Bring digital design, debugging, analytical, and communication skills to Qualcomm’s Ottawa ASIC engineering co-op program.

📌 Asic Design Verification Engineering Co Op Ottawa (Canada)
🏢 Qualcomm
📍 Canada