Lead Memory PHY DFT implementation at AMD in Markham, applying scan insertion and ATPG verification within Radeon Technologies Group.
As a technical lead supporting front-end design and integration, you will collaborate with architecture, IP design, Physical Design, and product engineering teams. The work focuses on achieving first pass silicon success through DFT architecture implementation, feature verification, and post-silicon support. Accuracy, detail orientation, communication, and problem-solving skills are significant.
Key Responsibilities:
- Implement and verify DFT architecture and features
- Perform scan insertion and generate ATPG patterns
- Verify ATPG patterns through gate-level simulation
- Analyze test coverage and reduce test costs
- Support post-silicon bring-up and yield learning
Requirements:
- Understand DFT methodologies and DFT verification
- Know IEEE1500, JTAG 1149.x, Scan, or memory BIST
- Use Mentor TestKompress or Synopsys TetraMAX/DFTMAX
- Experience VCS, Perl or Shell scripting, and Verilog RTL
- Bachelor's or Master's degree in computer or electrical engineering
Apply Memory PHY DFT leadership, scan expertise, and ATPG verification skills to AMD silicon development in Markham.