We're looking for a talented RTL Design Engineer with strong expertise in Verilog/SystemVerilog and PCIe protocol design/verification to join our growing team.

If you have a passion for digital design, micro-architecture development, and solving complex hardware challenges, we'd love to connect with you!

? Key Responsibilities:

- Develop and implement RTL designs using Verilog/SystemVerilog.
- Work on PCIe (Gen3/Gen4/Gen5) design and verification activities.
- Contribute to micro-architecture definition and RTL implementation.
- Perform debugging, validation, and performance optimization.
- Collaborate with cross-functional teams throughout the design lifecycle.

? Required Skills:

✅ Strong hands-on experience in RTL Design using Verilog/SystemVerilog

✅ Hands-on experience with PCIe protocols (Gen3/Gen4/Gen5 preferred)

✅ Solid understanding of digital design fundamentals:





- FSM Design
- Pipelining
- Clock Domain Crossing (CDC)
- Reset Architecture
- Synchronizers
- Low-Power Design Concepts

✅ Experience in micro-architecture development and RTL implementation ✅ Knowledge of synthesis constraints and timing concepts

✅ Familiarity with Lint, CDC, STA, and low-power verification methodologies

✅ Solid debugging and problem-solving skills

? Location: Canada

If you're interested or know someone who would be a great fit, please reach out directly or send your updated resume.

#RTLDesign #Verilog #SystemVerilog #PCIe #Semiconductor #VLSI #ASICDesign #HardwareEngineering #DigitalDesign #Hiring #CanadaJobs #HCLTech #TechCareers

📌 RTL Design Engineer (Canada)
🏢 HCLTech
📍 Canada