Own RTL CI/CD infrastructure for Eliyan’s NuLink chiplet interconnect technology, combining Jenkins, quality gates, and synthesis tracking onsite Monday through Friday.
This engineering role centers on reliable design-flow infrastructure across multiple concurrent IP programs. You will manage lint, CDC, RDC, elaboration, synthesis, and STA automation. You will also create dashboards, release gates, and evidence pipelines that help designers promote qualified branches.
Key Responsibilities: Optimize Jenkins-based RTL quality pipelines for turnaround time
Define release criteria, handoff checkpoints, and waiver management
Create dashboards exposing QoR regressions and responsible commits
Automate clean-run branch gating and release handoff evidence
Build annotated pull requests from filtered design violations
Requirements: Three-plus years in hardware, EDA, or infrastructure automation
Robust Python with Tcl, shell scripting, Git, Linux, and Makefiles
Experience debugging and rearchitecting Jenkins or comparable CI
Ability to read RTL front-end lint and CDC output
Onsite Monday through Friday at Bay Area, Vancouver, or Toronto
Bring CI/CD, RTL quality, QoR tracking, and release-gate expertise to Eliyan’s digital design organization.