Build AMD PCI Express IP with RTL, Verilog HDL, and subsystem integration expertise. Drive accurate, high-quality implementation across front-to-back design flows.

This ASIC Design Engineer role focuses on PCIe IP Enablement within AMD’s design organization. You will develop digital IP from architecture through tape-out, supporting implementation, verification-related closure, and SoC deployment. Collaboration spans IP designers, Physical Design teams, and SoC leads.

Key Responsibilities:

- Design and implement PCIe subsystem IP for SoC integration
- Drive RTL quality through lint, CDC, synthesis, LEC, and STA
- Support subsystem integration, ECO, SRAM generation, and repeaters
- Address clocks, testing, debugging, and design implementation needs




- Collaborate with multi-site engineers and managers on schedules

Requirements:

- Proficiency with RTL and Verilog HDL digital design
- Experience with integration and implementation of IPs to SoC
- Familiarity with RDC, equivalence checks, and static timing analysis
- Understanding of low-power techniques and power-aware checks
- Electrical Engineering or Computer Engineering degree preferred

Use RTL design, PCIe subsystem integration, and closure expertise to deliver robust ASIC IP at AMD.

📌 ASIC RTL Engineer PCI Express (Markham)
🏢 AMD
📍 Markham