Analyze NoC transactions, bandwidth, QoS, latency, and throughput for Qualcomm SoC validation. Work across pre-silicon emulation and post-silicon analysis. This engineering role supports the central Global SoC digital hardware organization responsible for overall silicon quality. You will collaborate with architects, designers, verification engineers, software engineers, and customers. The focus includes on-chip interconnects, bus architecture, transaction stress programs, FIFO behavior, memory hierarchy, and system performance. Key Responsibilities:

Write programs stressing upstream and downstream interconnect transactions Assess bandwidth, QoS, latency, throughput, and appropriate coverage Evaluate FIFO performance and functionality across designs Validate memory hierarchy, caches, coherency,



and consistency Support performance monitors, interrupt architecture, and debug architecture Requirements:

Digital design fundamentals and on-chip interconnect understanding Experience with NoCs, AXI, AHB, and FIFO designs Embedded systems expertise with C, C++, Python, and assembly Logical problem-solving focused on SoC system feature validation Eligible degree and related ASIC experience under stated pathways Use interconnect expertise, transaction analysis, memory knowledge, and structured programming to strengthen Qualcomm SoC silicon validation.

📌 SoC Interconnect Performance Validation Engineer (Markham)
🏢 QUALCOMM
📍 Markham