Lead I/O chiplet verification in Ottawa with SystemVerilog, UVM, and high-speed interface expertise. Hybrid arrangements may be considered for project needs. As a Senior I/O Chiplet Verification Engineer at BTA Design Services, you will verify blocks, subsystems, and chip-level functions. Translate requirements into measurable goals, create sign-off evidence, and collaborate with architecture, RTL, firmware, physical design, and IP partners. The work covers high-speed datapaths and firmware-controlled management functions. Key Responsibilities:

Build plans linking requirements, scenarios, coverage, platforms, and sign-off Develop reusable SystemVerilog and UVM verification environments Integrate vendor VIP and verify protocol and PHY connectivity Verify switching, datapaths, resets, latency, throughput,



and recovery Automate regressions, triage failures, and close coverage Requirements:

Ten or more years of hands-on ASIC verification experience Strong SystemVerilog, UVM, constrained-random, and testbench architecture skills Experience with high-speed interfaces, SoCs, networking ASICs, and chiplets Hands-on VIP integration, reference models, scoreboards, and assertions Robust scripting, regression automation, and configuration management skills Use SystemVerilog, UVM, and ASIC verification leadership to produce sign-off evidence for advanced I/O chiplet designs at BTA Design Services.

📌 Senior Chiplet Verification Engineer (Ahuntsic)
🏢 BTA Design Services
📍 Ahuntsic