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Senior FPGA Research Engineer Location: Vancouver, British Columbia, CA

Overview

Barco's Vancouver team is developing FPGA-based sensing and edge AI capabilities for industrial applications. We are looking for a hands‑on senior FPGA engineer to lead the sensor acquisition and aggregation architecture connecting distributed imaging sensors to an FPGA-based Edge AI compute module.

Your initial focus will be a distributed industrial imaging system: capturing synchronized images from multiple sensor nodes, transporting and aggregating their data, and delivering reliable streams for measurement and AI analysis. The architecture must balance throughput, timing, signal integrity, power, and cost per sensing node.

Your second major responsibility will be the development of the next iteration of our FPGA-based Edge AI compute module. You will lead FPGA architecture and accelerator‑interface implementation, and co‑develop the board with electronics and embedded‑software engineers. The goal is a production‑oriented system for workloads where validated throughput, power, and cost justify NPU deployment.

What You Will Do

Own FPGA architecture and RTL for sensor acquisition, synchronization, aggregation, and delivery to edge compute.

Implement and validate imaging‑sensor interfaces, including Sub‑LVDS/LVDS capture, deserialization, lane alignment, sensor timing, and configuration control.

Evaluate sensor‑side bridge logic and hub architectures; select practical multiplexing, framing, and transport approaches based on measured performance and total system cost.

Develop multi‑sensor pipelines with clock‑domain crossing, elastic buffering, timestamps, stream identification, packetization,



and explicit detection of missing or corrupted data.

Implement high‑speed serial links using suitable vendor transceiver IP, line coding, lane alignment, link monitoring, and recovery mechanisms.

Integrate FPGA data paths with memory and hardware DMA, working with embedded‑software engineers to deliver data to GPU/NPU processing pipelines.

Lead FPGA‑side architecture for the FPGA + NPU board, including device selection, resource and transceiver budgets, PCIe topology, memory architecture, and host‑control interfaces.

Co‑develop board requirements with electronics engineers, including clocks, resets, power sequencing, high‑speed routing constraints, debug access, and thermal and power budgets.

Implement and validate FPGA‑to‑NPU data movement, buffer management, flow control, and result handling using supported accelerator interfaces.

Work with embedded‑software engineers and accelerator vendors on PCIe enumeration, DMA integration, driver/runtime compatibility, and recovery from link or accelerator faults.

Evaluate host‑memory staging and direct‑transfer options where supported; measure actual throughput, latency, CPU overhead, and memory use rather than assuming a zero‑copy path.

Lead FPGA‑related board bring‑up and debug interface problems across RTL, PCB, firmware, and software boundaries.





Build self‑checking simulations and repeatable hardware tests; close timing and characterize throughput, latency, data integrity, resource use, and power.

Qualify representative sensor links and compute interfaces under realistic cable lengths, industrial noise, and sustained workload conditions.

Document design decisions, interface specifications, validation results, and production handover requirements.

Requirements

Substantial hands‑on FPGA development experience, typically 7+ years or equivalent depth, with ownership of complex designs through hardware validation.

Solid proficiency in VHDL or Verilog/SystemVerilog, synchronous design, clock‑domain crossing, reset design, timing constraints, and timing closure.

Experience acquiring data from imaging sensors or other high‑rate, source‑synchronous devices.

Experience designing high‑throughput, high‑frame‑rate multi‑camera video pipelines, including synchronized stream aggregation or image assembly/tiling, buffering and bandwidth budgeting, and transfer from sensor‑facing FPGA I/O to high‑speed serial links.

Practical experience with FPGA high‑speed transceivers and multi‑channel streaming systems.

Hands‑on Altera/Intel FPGA development experience using Quartus, preferably with Agilex or another SoC FPGA family.

Practical experience integrating FPGA PCIe interfaces and DMA engines, including hardware bring‑up and debugging data‑transfer problems.

Experience with memory interfaces, streaming interconnects such as AXI or Avalon, and throughput and buffering analysis across device boundaries.

Experience collaborating on custom FPGA boards, including schematic reviews, interface const

📌 Senior FPGA Research Engineer (Vancouver)
🏢 Barco
📍 Vancouver