Lead high-speed analog design for Synopsys Ser Des IP, combining CMOS fundamentals, circuit verification, and cross-functional collaboration with digital and layout engineers. Mentor technical talent.This senior design leader will develop robust analog macros for advanced connectivity standards and guide implementation from architecture through testing. You will refine circuit solutions, oversee physical layout, and coordinate calibration, adaptation, and control work with digital RTL engineers. The role requires deep Ser Des sub-circuit knowledge and practical silicon experience.Key Responsibilities:



Develop analog macros across Ser Des architecture and implementationOversee layout impacts from parasitics and process variationCoordinate analog circuits with digital control algorithmsExecute verification strategies using advanced simulator featuresMentor junior engineers and review their progressRequirements: Ph D with 10+ years or MSc with 12+ years’ experienceDeep knowledge of equalizers, samplers, drivers, and PLLsAdvanced Fin FET CMOS layout optimization skillsAwareness of ESD and reliability techniquesProgramming experience with TCL, Perl, C, Python, and MATLABBring high-speed analog leadership, Ser Des expertise, layout awareness, and verification discipline to Synopsys IP engineering.#J-18808-Ljbffr

📌 High-Speed Analog Serdes Design Leader (Winnipeg)
🏢 Synopsys
📍 Winnipeg