Job Title: Design Verification Engineer Client: NeurealM/ Microchip Location: Vancouver, BC, Canada - Initial 1 month Hybrid then after Remote Job Type: Contract Job Summary We are looking for a Design Verification Engineer with robust experience in ASIC/SoC verification to develop and execute verification settings and ensure high-quality digital designs.

Responsibilities Develop verification environments and testbenches using System

Verilog and UVM.

Create and execute functional, regression, and constrained-random tests.

Analyze functional/code coverage and drive coverage closure.

Debug RTL and simulation failures and work with design teams to resolve issues.

Verify protocols such as AMBA/AXI, PCIe, Ethernet, or similar interfaces.

Automate testing and regression using Python, Perl, or Shell scripting.

Required Skills Strong System

Verilog & UVM experience.

Solid understanding of RTL, digital design, and ASIC/SoC verification.

Experience with simulation tools such as VCS, Xcelium, or Questa.

Solid debugging and scripting skills.

Bachelor's/Master's degree in Electrical, Electronics, or Computer Engineering.

📌 Design Verification Engineer Vancouver
🏢 Diligent Tec
📍 Vancouver