Position: Analog Layout EngineerExperience: 5 to 15 YearsLocation: Ottawa, CanadaJob Type: Full-Time / PermanentWork Model: OnsiteRole OverviewWe are seeking a skilled Analog Layout Engineer with strong hands-on experience in advanced nodes (TSMC 3nm or 5nm) to join our layout design team in Canada. The ideal candidate will have a solid background in the layout of analog and mixed-signal circuits for high-performance So Cs and IPs.Key ResponsibilitiesExecute full custom layout of analog and mixed-signal blocks (e.G., op-amps, bandgaps, comparators, LDOs, PLLs, data converters)Participate in floorplanning, placement, routing, and optimization of analog blocksDrive layout closure with designers across multiple PVT cornersEnsure compliance with DRC, LVS, ERC, and EM/IR requirementsCollaborate with circuit designers to address layout-dependent effects (LDE), parasitic extraction (PEX), and performance-sensitive layoutDeliver layout for TSMC 3nm/5nm technologies, meeting aggressive area, power,



and performance goalsRequired Skills5+ years of experience in analog/mixed-signal layoutHands-on experience with TSMC 5nm or 3nm process nodesProficient in using Cadence Virtuoso layout tools (XL/GXL)Solid understanding of matching, shielding, parasitics, and analog layout best practicesExperience with PEX (Parasitic Extraction) and post-layout simulation collaborationFamiliarity with Calibre/Assura for DRC, LVS, and physical verificationGood to HaveExperience with EM/IR analysis tools (e.G., Voltus-Fi)Scripting skills (Skill, Python, or Tcl)Background in layout automation techniquesExposure to high-speed layout (Ser Des, DDR, PLLs)Why Join UsOpportunity to work on leading-edge 3nm/5nm analog IPsCollaborative work environment with exposure to world-class So C teamsCompetitive compensation and career growth path#J-18808-Ljbffr

📌 Senior Analog Layout Engineer (Quebec City)
🏢 leadIC Design
📍 Quebec City