Apply Verilog HDL and RTL quality expertise to AMD PCI Express subsystem integration, synthesis, timing, lint, and CDC closure.
This ASIC Design Engineer role centers on PCIe IP Enablement across architecture, IP design, implementation, and SoC integration. You will help deliver accurate, high-quality designs while working with IP designers, Physical Design teams, and SoC-level leads. The position includes technical problem-solving, debugging, and flow automation.
Key Responsibilities: Design and develop PCIe IP and related digital subsystems
Drive synthesis, lint, CDC, equivalence, and timing closure
Support subsystem integration, implementation, and SoC deployment
Implement clock, test, and debug-related design requirements
Identify technical issues and guide solution direction
Requirements: Proven ASIC design experience through architecture to tape-out
Robust understanding of RTL and Verilog HDL
Experience with RTL quality and design flow tools
Understanding of power-saving techniques and power-aware checks
Excellent problem-solving, communication, and debugging skills
Use PCIe, RTL, synthesis, CDC, and subsystem integration skills to advance AMD digital design programs.

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📌 PCI Express RTL Design Engineer (Ontario)
🏢 Advanced Micro Devices
📍 Ontario