Lead high-speed analog design for Synopsys Ser Des IP, combining CMOS fundamentals, circuit verification, and cross-functional collaboration with digital and layout engineers. Mentor technical talent.
This senior design leader will develop robust analog macros for advanced connectivity standards and guide implementation from architecture through testing. You will refine circuit solutions, oversee physical layout, and coordinate calibration, adaptation, and control work with digital RTL engineers. The role requires deep Ser Des sub-circuit knowledge and practical silicon experience.
Key Responsibilities: Develop analog macros across Ser Des architecture and implementation
Oversee layout impacts from parasitics and process variation




Coordinate analog circuits with digital control algorithms
Execute verification strategies using advanced simulator features
Mentor junior engineers and review their progress
Requirements: Ph D with 10+ years or MSc with 12+ years’ experience
Deep knowledge of equalizers, samplers, drivers, and PLLs
Advanced Fin FET CMOS layout optimization skills
Awareness of ESD and reliability techniques
Programming experience with TCL, Perl, C, Python, and MATLAB
Bring high-speed analog leadership, Ser Des expertise, layout awareness, and verification discipline to Synopsys IP engineering.

📌 High-speed Analog Serdes Design Leader (Winnipeg)
🏢 Synopsys
📍 Winnipeg