System Verilog and UVM expertise meet NVIDIA’s High Speed Coherent Interconnect Hub verification work in a senior engineering position.As a Senior Verification Engineer, you will support Tegra So C IP Verification by working with architecture and design teams. You will verify complex interconnect IP through constrained-random and coverage-driven methodologies. The work includes protocol compliance, performance validation, debugging, and design signoff.Key Responsibilities: Develop testbenches, BFMs, checkers, monitors, scoreboards, and assertionsDefine verification plans for coherency, ordering, errors, and performanceVerify interoperability across So C and multi-chip interfacesValidate bandwidth, latency, Qo S,



and traffic requirementsDrive coverage closure and verification signoffRequirements: BS, MS, or equivalent experienceThree-plus years verifying complex ASIC IPs or So C subsystemsStrong System Verilog, UVM, and constrained-random verification backgroundExperience developing verification environments, checkers, assertions, and coverageStrong debugging skills using industry-standard simulation toolsApply coherent interconnect verification, UVM, debugging, and coverage expertise to NVIDIA’s next-generation computing platforms.#J-18808-Ljbffr

📌 Senior Coherent Interconnect Verification Engineer (Toronto)
🏢 NVIDIA
📍 Toronto