Design advanced Ethernet IP at NXP in Ottawa, using Verilog RTL and micro-architecture for next-generation automotive, industrial, and edge SoCs. As a Logic Design Engineer, you will architect and implement networking IP within Advanced Chip Engineering. Your work covers RTL design, synthesis, timing closure, and performance, area, and complexity trade-offs. You will support IP quality and delivery.

Key Responsibilities
Architect and implement Ethernet and networking IP Develop micro-architecture and Verilog RTL implementations Perform synthesis, timing closure, and design trade-off analysis Complete Lint, CDC, STA, and LEC quality checks Support reviews, planning, verification, and documentation

Requirements:
Bachelor’s degree in Computer Science, Engineering, or related education Knowledge of Verilog RTL, synthesis, coverage, and timing closure Understanding of IP development methodology and front-end design tools Solid communication, documentation, and interpersonal skills Ability to solve system-wide problems and work within teams Apply hardware design, networking, and verification knowledge to develop implementation-ready IP with NXP’s Ottawa engineering team. #J-18808-Ljbffr

📌 Design Analysis Engineer (Ottawa)
🏢 NXP Semiconductors
📍 Ottawa