Apply SystemVerilog UVM and security verification expertise at Arm, with hybrid working patterns determined by team needs. Help validate security IP for pioneering SoC designs. As a Design Verification Engineer, you will work on cryptography, key management, embedded microprocessor systems, hardware root of trust, and secure boot. You will help define and realize hardware security IP and subsystems. The work spans test planning, testbench development, verification models, test strategies, and productization. You will partner with design teams for functional sign off, comprehensive coverage, and power and performance optimization. Key Responsibilities:

Craft test plans and verification strategies for security IP Develop UVM, SystemVerilog, Verilog,



and C testbenches Debug test failures and verification issues Partner with design teams on functional sign off Mentor team members and support project initiatives Requirements:

Three-plus years verifying sophisticated IP, subsystems, or SoCs Bachelor’s or Master’s degree in a related field Understanding of Verilog HDL and SystemVerilog UVM Experience with security hardware, cryptography, and secure boot Experience with Python, Perl, Tcl, or similar scripting Bring security hardware, UVM, and embedded verification expertise to Arm’s Hardware Security IP development and SoC programs.

📌 Security Design Verification Engineer (Winnipeg)
🏢 Arm
📍 Winnipeg