Shape PLL and timing circuitry at SiTime, combining phase-noise knowledge, transistor analysis, and hands-on prototype characterization for advanced products.This Staff Analog Design Engineer develops analog circuits and key blocks for high-performance timing products. The work requires understanding transistor behavior, circuit noise theory, phase-noise concepts, and top-level architecture. You will support silicon development, product validation, qualification, release, and customer applications through cross-functional collaboration.Key Responsibilities:




Design PLLs and supporting analog timing circuitsIncorporate circuit blocks into complete chip designsTest and debug laboratory prototypesCharacterize prototypes and support product validationSupport qualification and current product releaseRequirements:
Master’s or PhD degree in Electrical EngineeringSix or more years of relevant analog or mixed-signal IC designKnowledge of device physics and advanced process technologiesUnderstanding of transistor behavior, noise, and phase noiseHands-on laboratory testing and characterization experienceApply PLL, phase-noise, and analog circuit expertise to SiTime’s MEMS-based precision timing technology development.
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📌 Staff Pll Analog Design Engineer (Riviere-des-Prairies—Pointe-aux-Trembles)
🏢 SiTime
📍 Riviere-des-Prairies—Pointe-aux-Trembles