SystemVerilog and UVM expertise drives ASIC verification at Qualcomm Canada ULC. Build reliable connectivity technology for high performance products.
As a Senior Verification Engineer, you will verify digital and analog mixed signal designs within Qualcomm’s HSI Digital Design Verification team. The team develops high speed SerDes technology for communication among compute, memory, storage, and networking components. Your work spans testbench development, simulation debugging, protocol compliance, and verification closure. Collaboration with Design, Systems, Firmware, and Analog teams supports product execution.
Key Responsibilities: Review specifications and create verification plans for design functionality
Develop SystemVerilog and UVM testbenches and test cases
Debug simulations and identify root causes




Integrate analog models and third-party protocol verification IP
Support post-silicon chip bringup and verification closure
Requirements: Bachelor’s degree and two-plus years of relevant ASIC experience
Proficiency with SystemVerilog, UVM, and constrained random verification
Experience developing and maintaining verification environments
Knowledge of Ethernet and PCIe standards is desirable
Python, Perl, C/C++, and GNU Make experience
Apply ASIC verification, SystemVerilog, and UVM expertise to advance SerDes connectivity at Qualcomm Canada ULC.

#J-18808-Ljbffr

📌 Senior ASIC Verification Engineer (Ontario)
🏢 QUALCOMM
📍 Ontario