Join the leading chiplet startup! As an Eliyan Verification Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art AMS System Verilog models (RNM) for best-in-class PHYs. You will own verification of AMS System Verilog models. This is a hands-on technical role. You'll work with analog team, look at schematics and write the RNM models. We offer a fun work environment with excellent advantages. We offer a fun work environment with excellent benefits.



ONSITE M-F.Key Responsibilities:Develop and execute RNM AMS model for best in class PHYs.Make sure the quality of models reflects schemetics.Write and debug System Verilog/UVM compliant test casesCollaborate with design team to ensure design qualityExpertise to understand analog blocks.Required Qualifications:5+yrs relevant experienceBS in EE or related field.Deepanalog design expertiseKnowledge of System Verilog, test environment and assertion codingExperience in verifying mixed signal IPsPreferred Qualifications:Experience with Formal verification with Jasper Gold or vc-formalPython/Perl/Tclscripting for design verification#J-18808-Ljbffr

📌 Dv - Staff (+) Verification Engineer- Ams Modeling (Toronto)
🏢 Eliyan
📍 Toronto