Design advanced Ethernet IP in Ottawa using Verilog RTL, synthesis, and timing closure for next-generation automotive and industrial SoCs.
As a Logic Design Engineer at NXP, you will architect and implement networking IP for microcontrollers and microprocessors. Your work spans micro-architecture, RTL design, implementation trade-offs, and front-end quality checks. You will collaborate with verification, integration, software, architecture, marketing, and application engineering teams.
Key Responsibilities: Architect and implement Ethernet and networking IP
Develop micro-architecture and Verilog RTL implementations
Perform synthesis, timing closure, and design trade-off analysis
Complete Lint, CDC, STA, LEC, and other quality checks
Support code reviews, planning, documentation,



and continuous improvement
Requirements: Bachelor’s degree in Computer Science, Engineering, or related education
Knowledge of Verilog RTL, synthesis, coverage analysis, and timing closure
Understanding of IP development methodology and front-end design tools
Ability to solve system-wide problems and assess hardware-software trade-offs
Solid interpersonal, communication, documentation, and teamwork skills
Bring RTL design, networking knowledge, and architecture skills to NXP’s Ottawa engineering team developing implementation-ready Ethernet IP.

#J-18808-Ljbffr

📌 Ethernet IP Design Engineer (Quebec City)
🏢 NXP Semiconductors
📍 Quebec City