Use SystemVerilog and Python to validate complex SoC designs as a Pre-Silicon Emulation Engineer with Qualcomm Technologies in San Diego, onsite. Hardware emulation and RTL debugging anchor this engineering work. This Junior/Senior Emulation Engineer supports ASIC and FPGA-based design development and validation. You will build emulation environments, enable hardware/software co-validation, and apply system-level debugging. The work spans verification infrastructure, automation, waveform analysis, and AI-assisted productivity tools. Key Responsibilities:

Develop and maintain ASIC and FPGA emulation environments Port RTL onto Palladium, Veloce, or FPGA platforms Build testbenches and transactors using SystemVerilog and C/C++ Debug functional, performance,



and system-level emulation issues Create Python automation workflows for regressions and debugging Requirements:

Bachelor's or Master's degree in a related technical field Zero to two or more years in verification, prototyping, or emulation Expertise with SystemVerilog, C/C++, Linux, shell scripting, and Python Experience with RTL debugging and waveform analysis Knowledge of SoC architectures, bus protocols, and hardware/software interactions Apply emulation, RTL verification, Python automation, and system-level debugging to Qualcomm SoC validation in San Diego.

📌 Pre-Silicon Emulation Validation Engineer (Markham)
🏢 QUALCOMM
📍 Markham