Lead System Verilog and UVM verification for NXP networking IP, supporting advanced microcontrollers, processors, and switches across major markets.As a Principal Design Verification Engineer, you will verify Ethernet and networking IP for next-generation So Cs. You will architect UVM verification infrastructure, execute complete verification cycles, and collaborate with architecture, design, and verification teams. The work supports automotive, industrial, and edge computing products.Key Responsibilities: Verify Ethernet and networking IP for next-generation So CsArchitect and implement UVM verification for IP and So CsBuild directed and random verification testsDebug failures and resolve defects with design engineersReview coverage and improve verification methodologyRequirements: 10+ years of IP and So C experienceExpertise in System Verilog and UVM verificationExperience with EDA tools and verification scriptingProficiency with Python, TCL, Perl, Makefile, and ShellBachelor's degree in Computer Science or EngineeringApply your principal-level verification expertise to Ethernet IP, UVM infrastructure, coverage, and So C quality at NXP.#J-18808-Ljbffr

📌 Principal Ethernet Design Verification Engineer (Quebec City)
🏢 NXP Semiconductors
📍 Quebec City