Advance AMD PCIe solutions through ASIC design, RTL implementation, and IP enablement. Collaborate across teams on power-effective, performance-optimized designs.As an ASIC Design Engineer, PCIe IP Enablement, you will contribute across architecture, IP design, RTL, and front-to-back flows. You will own complex digital IP and subsystems from architecture through tape-out. The work includes So C integration, quality closure, and design direction.Key Responsibilities: Integrate AMD PCI Express subsystems and deploy IP to So CsComplete synthesis, timing, lint, and CDC closureImplement test, debug, and clock-related design workApply UPF-based power-aware design flows and techniquesDevelop automation and scripting for hands-on flow improvementRequirements: Digital design experience using RTL and Verilog HDLExperience with synthesis, linting, CDC tools, and equivalence checksKnowledge of UPF or CPF power-aware flowsBachelor's or Master's degree in Electrical or Computer EngineeringStrong problem-solving, debugging, and communication skillsApply ASIC design expertise, PCIe integration, RTL quality flows, and power-aware techniques to AMD IP enablement.#J-18808-Ljbffr

📌 Pcie Ip Asic Design Engineer (Markham)
🏢 AMD
📍 Markham