SystemVerilog and UVM expertise meet NVIDIA’s High Speed Coherent Interconnect Hub verification work in a senior engineering position. As a Senior Verification Engineer, you will support Tegra SoC IP Verification by working with architecture and design teams. You will verify complex interconnect IP through constrained-random and coverage-driven methodologies. The work includes protocol compliance, performance validation, debugging, and design signoff.
Key Responsibilities
Develop testbenches, BFMs, checkers, monitors, scoreboards, and assertions Define verification plans for coherency, ordering, errors, and performance Verify interoperability across SoC and multi-chip interfaces Validate bandwidth, latency, QoS,
and traffic requirements Drive coverage closure and verification signoff
Requirements:
BS, MS, or equivalent experience Three-plus years verifying complex ASIC IPs or SoC subsystems Strong SystemVerilog, UVM, and constrained-random verification background Experience developing verification environments, checkers, assertions, and coverage Robust debugging skills using industry-standard simulation tools Apply coherent interconnect verification, UVM, debugging, and coverage expertise to NVIDIA’s next-generation computing platforms.