Architect and verify Ethernet networking IP at NXP with System Verilog and UVM expertise. Develop So C technology for automotive, industrial, and edge markets.As a Design Verification Engineer, you will develop networking switch and network controller IP supporting current TSN standards. Your work covers hardware IP and System on Chip products within NXP’s AI and Chip Engineering organization. You will build verification infrastructure, execute full verification cycles, and help deliver high-quality IP for multiple markets.Key Responsibilities:



Architect and verify Ethernet networking IP for next-generation So CsImplement UVM verification for hardware IP and So C productsBuild directed and random verification testsDebug failures and resolve defects with engineering teamsReview coverage metrics and improve verification methodologyRequirements: Five or more years’ experience with IP and So C productsThorough System Verilog and UVM verification expertiseProficiency with verification tools and EDA scriptingExperience with Python, TCL, Perl, Makefile, Shell, and GitBachelor’s degree in Computer Science, Engineering, or related fieldApply Ethernet IP verification, UVM, System Verilog, and coverage expertise to NXP networking So C development.#J-18808-Ljbffr

📌 Senior Ethernet Ip Verification Engineer (Quebec City)
🏢 NXP Semiconductors
📍 Quebec City