Lead HUB and Router verification at AMD, applying system architecture expertise and AI-enabled methods to complex silicon designs. The position is full-time.As Principal Design Verification Engineer, you will provide technical leadership for AMD’s IOHUB front-end IP verification team. You will define scalable verification strategies, collaborate across architecture, design, emulation, firmware, and AI tooling, and improve productivity through automation and data-driven methods. The work supports server, data center, client, and embedded products.Key Responsibilities: Own HUB and Router design verification test plans and methodologiesBuild end-to-end strategies with architecture and engineering partnersLead AI-assisted regression, coverage, stimulus, and debug initiativesGuide usable workflows, success metrics,
and responsible tool adoptionMentor engineers and address verification closure risks earlyRequirements: Robust design verification expertise in architecture or related areasExperience with AI-enabled engineering workflows is valuedKnowledge of scripting, data analysis, or automation frameworksCommand of coverage-driven, constrained-random, formal, and emulation methodsBachelor’s or Master’s degree in a related engineering disciplineApply design verification leadership, AI-enabled engineering, and system architecture expertise to advance AMD IOHUB silicon verification.#J-18808-Ljbffr