Celero Communications is seeking an experienced ASIC Design Engineer to join our quick-growing semiconductor startup in Ottawa. You will design and implement high-performance digital circuits and ASIC blocks using Verilog/System Verilog, with exposure to DSP, Ser Des, and mixed-signal interfaces.You will collaborate with Analog, Verification, and Physical Design teams, perform synthesis and timing analysis, develop automation scripts in Python or Tcl, and help drive silicon bring-up from RTL#J-18808-Ljbffr