Shape the future of AI with a Principal Ser Des Design Engineer role, focused on high-speed interconnect technologies and next-gen transceiver architecture. Make an impact in a cutting-edge field.
In this senior position, you will define the architecture and specifications for next-generation Ser Des and lead the design of critical blocks. Your expertise will involve overseeing system-level modeling with advanced tools such as MATLAB and System Verilog, and designing high-performance analog/mixed-signal circuits in advanced node technologies.
Key Responsibilities:
• Define architecture and circuit topologies for Ser Des
• Oversee system-level modeling and behavioral analysis
• Design analog/mixed-signal circuits at advanced nodes




• Manage the design of RX/TX equalization circuits
• Lead lab validation and characterization of Ser Des IPs
Requirements:
• Master’s or Ph D in Electrical Engineering
• 10+ years of Ser Des design experience
• Proven record in high-speed design tape-out
• Extensive background in advanced node technologies
• Solid cross-functional collaboration and communication skills
Bring your innovative design skills and experience to deliver transformative Ser Des solutions in this Principal role.

📌 Lead serdes designer for ai technology (Vancouver)
🏢 CELERO COMMUNICATIONS
📍 Vancouver