Build AI-augmented RTL quality automation at Eliyan, using Python and Jenkins onsite Monday through Friday in the Bay Area, Vancouver, or Toronto.

As a Digital and ASIC Design Automation Engineer, you will own Jenkins-based CI across active design programs. Your work spans lint, CDC, synthesis, STA, Git, Linux, and SystemVerilog. You will develop applied LLM tooling that makes design-flow decisions faster and clearer.

Key Responsibilities:

- Own Jenkins CI for RTL lint, CDC, RDC, synthesis, and STA
- Build automated branch qualification and release promotion evidence
- Track synthesis and timing results through project dashboards
- Develop LLM pipelines for violation triage and clustering
- Implement spec-to-RTL consistency and documentation checks

Requirements:

- BS or MS in engineering, computer science, or related field
- Three-plus years building automation, CI/CD, or engineering tooling
- Solid Python, Tcl, shell scripting, Git, Linux, and Makefiles
- Hands-on Jenkins or GitLab CI or GitHub Actions experience
- Working RTL front-end, SystemVerilog, and LLM API knowledge

Apply digital design automation, Jenkins, Python, and practical LLM engineering to Eliyan’s RTL development infrastructure onsite.

📌 Digital Design Automation Engineer (Toronto)
🏢 Eliyan
📍 Toronto