Celero Communications, Inc. in Ottawa is seeking an experienced ASIC Design Engineer to contribute to high‑speed optical communication ASICs. You will design digital blocks in Verilog/SystemVerilog, integrate DSP, SerDes, and mixed‑signal components, and collaborate across Analog, Verification, and Physical Design to deliver silicon through tapeout. You will perform synthesis, timing analysis, CDC, and lint, drive PPA optimizations, write automation in Python or Tcl, and guide other engineers in