Architect and verify Ethernet networking IP at NXP with System Verilog and UVM expertise. Develop So C technology for automotive, industrial, and edge markets.
As a Design Verification Engineer, you will develop networking switch and network controller IP supporting current TSN standards. Your work covers hardware IP and System on Chip products within NXP’s AI and Chip Engineering organization. You will build verification infrastructure, execute full verification cycles, and help deliver high-quality IP for multiple markets.
Key Responsibilities: Architect and verify Ethernet networking IP for next-generation So Cs
Implement UVM verification for hardware IP and So C products
Build directed and random verification tests




Debug failures and resolve defects with engineering teams
Review coverage metrics and improve verification methodology
Requirements: Five or more years’ experience with IP and So C products
Thorough System Verilog and UVM verification expertise
Proficiency with verification tools and EDA scripting
Experience with Python, TCL, Perl, Makefile, Shell, and Git
Bachelor’s degree in Computer Science, Engineering, or related field
Apply Ethernet IP verification, UVM, System Verilog, and coverage expertise to NXP networking So C development.

📌 Senior ethernet ip verification engineer (Quebec City)
🏢 NXP Semiconductors
📍 Quebec City