26 Oct
|
CELERO COMMUNICATIONS
|
Quebec City
26 Oct
CELERO COMMUNICATIONS
Quebec City
Celero Communications, Inc. in Ottawa is seeking an experienced ASIC Design Engineer to contribute to high‑speed optical communication ASICs.
You will design digital blocks in Verilog/System Verilog, integrate DSP, Ser Des, and mixed‑signal components, and collaborate across Analog, Verification, and Physical Design to deliver silicon through tapeout. You will perform synthesis, timing analysis, CDC, and lint, drive PPA optimizations, write automation in Python or Tcl, and guide other engineers in
📌 Senior asic design engineer (Quebec City)
🏢 CELERO COMMUNICATIONS
📍 Quebec City