Design AMD PCIe solutions through RTL implementation and front-to-back flows, contributing to power-productive, performance-optimized ASIC development.As an ASIC Design Engineer focused on PCIe IP Enablement, you will support architecture, IP design, RTL implementation, and So C deployment. The work requires digital design expertise, Verilog HDL, and end-to-end ownership of complex digital IP or subsystems. You will collaborate across IP design, Physical Design, and So C teams.Key Responsibilities: Integrate AMD PCI Express subsystems and deploy IP to So CsComplete synthesis, timing, lint, and CDC closureImplement test, debug, and clock-related design elementsApply UPF-based power-aware design flows and checksDevelop automation, scripting, and design flows hands-onRequirements: ASIC hardware design experience with end-to-end ownershipStrong digital RTL design and Verilog HDL knowledgeExperience with synthesis, lint, CDC, equivalence, and STAKnowledge of low-power techniques and UPF or CPF flowsBachelor's or Master's degree in Electrical or Computer Engineering preferredBring PCIe integration, RTL quality, power-aware design, and technical problem-solving expertise to AMD ASIC development.#J-18808-Ljbffr