Lead digital ASIC design at Celero Communications using Verilog, SystemVerilog, and high-speed communication expertise for optical systems. As a Senior ASIC Design Engineer, you will develop advanced ASICs for optical connectivity, transceivers, and modems. The work spans RTL design, DSP, SerDes, digital communications, and mixed-signal integration. You will contribute across architecture, implementation, verification, tapeout, and silicon validation.

Key Responsibilities
Design digital circuits and ASIC blocks using Verilog and SystemVerilog Integrate DSP, digital communication, and SerDes functionality Develop high-speed data paths and optical communication interfaces Perform synthesis, timing analysis, lint, CDC,



and formal equivalence Optimize performance, power, and area across ASIC designs

Requirements:
~ Master’s or Ph.
D. in Electrical or Computer Engineering ~10+ years of digital ASIC design experience ~ Solid proficiency in Verilog and/or SystemVerilog ~ Experience with ASIC flows and industry-standard EDA tools ~ Knowledge of DSP, SerDes, analog, or optical communications Apply senior digital ASIC expertise across Verilog, DSP, SerDes, and optical communication products at Celero Communications. #J-18808-Ljbffr

📌 Senior Digital Design Engineer (Ottawa)
🏢 CELERO COMMUNICATIONS
📍 Ottawa