25 Oct
|
CELERO COMMUNICATIONS
|
Quebec City
25 Oct
CELERO COMMUNICATIONS
Quebec City
Celero Communications, Inc. is seeking an ASIC Design Engineer to join our quick-growing Ottawa team. You will design high-performance digital ASICs for optical communication systems, using Verilog/System Verilog and collaborating with DSP, Ser Des, and analog teams.
You will drive from architecture through tapeout, perform synthesis and timing analyses, optimize for PPA, and develop automation scripts in Python/Tcl to streamline design flows in a startup environment.
📌 Optical dsp (Quebec City)
🏢 CELERO COMMUNICATIONS
📍 Quebec City