Ciena is seeking a Digital Verification Engineer (FEC) in Ottawa to lead verification of Forward Error Correction IP. You will develop verification plans, validate architectural blocks, and collaborate with ASIC teams to ensure robust design verification through simulation, formal methods, and coverage-driven approaches.
The role requires 10+ years in verification, a BS in Electrical/CS/Software, and robust skills in C/C++, SystemVerilog, UVM, SVA, and simulators.
📌 Principal Digital Verification Lead, FEC (Ottawa)
🏢 Ciena
📍 Ottawa