Lead SystemVerilog and UVM verification for NXP networking IP, supporting advanced microcontrollers, processors, and switches across major markets. As a Principal Design Verification Engineer, you will verify Ethernet and networking IP for next-generation SoCs. You will architect UVM verification infrastructure, execute complete verification cycles, and collaborate with architecture, design, and verification teams. The work supports automotive, industrial, and edge computing products. Key Responsibilities:

Verify Ethernet and networking IP for next-generation SoCs Architect and implement UVM verification for IP and SoCs Build directed and random verification tests Debug failures and resolve defects with design engineers Review coverage and improve verification methodology Requirements:

10+ years of IP and SoC experience Expertise in SystemVerilog and UVM verification Experience with EDA tools and verification scripting Proficiency with Python, TCL, Perl, Makefile, and Shell Bachelor's degree in Computer Science or Engineering Apply your principal-level verification expertise to Ethernet IP, UVM infrastructure, coverage, and SoC quality at NXP.

📌 Principal Ethernet Design Verification Engineer (Ahuntsic)
🏢 NXP Semiconductors
📍 Ahuntsic