Lead digital ASIC design at Celero Communications using Verilog, SystemVerilog, and high-speed communication expertise for optical systems.As a Senior ASIC Design Engineer, you will develop advanced ASICs for optical connectivity, transceivers, and modems. The work spans RTL design, DSP, SerDes, digital communications, and mixed-signal integration. You will contribute across architecture, implementation, verification, tapeout, and silicon validation.Key Responsibilities:
Design digital circuits and ASIC blocks using Verilog and SystemVerilogIntegrate DSP, digital communication, and SerDes functionalityDevelop high-speed data paths and optical communication interfacesPerform synthesis, timing analysis, lint, CDC, and formal equivalenceOptimize performance, power, and area across ASIC designsRequirements:
Master’s or Ph.D. in Electrical or Computer Engineering10+ years of digital ASIC design experienceStrong proficiency in Verilog and/or SystemVerilogExperience with ASIC flows and industry-standard EDA toolsKnowledge of DSP, SerDes, analog, or optical communicationsApply senior digital ASIC expertise across Verilog, DSP, SerDes, and optical communication products at Celero Communications.
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📌 Senior Digital Asic Design Engineer (Riviere-des-Prairies—Pointe-aux-Trembles)
🏢 CELERO COMMUNICATIONS
📍 Riviere-des-Prairies—Pointe-aux-Trembles