Shape Ser Des IP architecture at Synopsys through transistor-level design, advanced verification, and technical leadership across analog macro circuits. Mentor engineers while optimizing high-speed interfaces.As an experienced Analog Circuit Architect, you will own analog macro-level circuits for Ser Des IP and guide sub-block progress. You will interpret standards, define specifications, and balance power, area, and performance. The work spans silicon-proven TX, RX, and clock paths, Fin FET CMOS layout, SPICE analysis, and Verilog-A modeling.Key Responsibilities: Own Ser Des analog macro architecture, design, and implementationTrack sub-block owners and review technical progressTranslate standards into detailed analog specificationsOptimize circuits for power,



area, and performancePresent simulations and insights during peer and customer reviewsRequirements: Ph D with 10+ years or MSc with 12+ years’ experienceExpertise in transistor-level and CMOS circuit designSilicon-proven TX, RX, and clock path implementationLeadership experience guiding small design teamsProficiency with EDA tools, SPICE, and Verilog-AApply your Ser Des architecture, analog design, verification, and leadership expertise to Synopsys semiconductor IP development.#J-18808-Ljbffr

📌 Senior Serdes Analog Circuit Architect (Winnipeg)
🏢 Synopsys
📍 Winnipeg