Principal Analog Layout Design Engineer/Lead Senior/Principal High-Speed Analog Layout Design Engineer About the Role Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture. We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems.

As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.

Key Responsibilities - Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification - Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability - Mentor and guide junior layout engineers/contractors across multiple time zones,



enforcing best practices in layout design and verification - Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.) - Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing - Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence - Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus) Required Qualifications - Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies - Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design - Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred) - At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16) - Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance - Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry,



and parasitic minimization - Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design - Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools - Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules - Experience working in collaborative environments with international and remote teams - Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams - Experience using revision control systems for layout design management Preferred Qualifications - Exposure to optical or high-speed analog interfaces is a strong plus - Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization - Proven ability to collaborate with international teams (U.S., Canada, Argentina) - Solid organizational skills with high attention to detail and follow-through - Ability to multi-task and prioritize in a fast-paced, dynamic environment - Proactive, eager-to-learn mindset with excellent problem-solving skills What We Offer - The chance to play a foundational role at a high-growth semiconductor start-up - Exposure to a wide variety of cross functional teams - A collaborative, international team culture where ideas and initiative are valued - The opportunity to grow alongside Celero as we scale and shape the future of our industry - A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity

📌 Principal Analog Layout Design Engineer/Lead (Ottawa)
🏢 CELERO COMMUNICATIONS
📍 Ottawa