Lead AMD graphics physical design for next-generation AI data center chips in Vancouver or Markham, using timing closure and advanced processes. This senior engineer owns complex multi-million-gate graphics IP blocks from floorplanning through final signoff. You will partner with RTL design teams throughout delivery. The work includes synthesis, placement, routing, physical verification, and optimization across performance, power, and area. Technical leadership and mentorship are central to the position. Own physical design for complex multi-million-gate graphics IP blocks Drive performance, power, and area optimization toward required targets Improve methodologies, automated flows, and design-quality checks Solid high-performance semiconductor physical design experience Proficiency with Python and TCL for design-flow automation Experience leading engineers through design closure and mentoring Bachelor’s or Master’s in Electronics or Electrical Engineering preferred Apply physical design, timing closure, and technical leadership expertise to AMD graphics IP delivery in Canada. #