At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars, machine learning to artificial intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation. We develop and deliver industry-leading high-speed interface IP and system solutions, enabling customers to build reliable, high-performance products across advanced nodes and packaging technologies. With a proven track record in end-to-end SIPI for advanced links such as PCI Express (Gen6/7/8), E224G, E448G, and CXL (over PCIe), you thrive on solving complex engineering challenges and collaborating across cross-functional teams.

You have a strong foundation in electromagnetic theory, transmission lines, and advanced modeling, and you are adept at translating system requirements into actionable, measurable signoff criteria. Your expertise spans both theoretical and practical realms: you are comfortable with channel modeling, frequency and time domain analysis, and using state-of-the-art simulation and measurement tools. You bring hands-on experience in bench characterization, compliance testing, and fixture design, always striving for rigorous correlation between simulation and hardware.

As a technical leader, you mentor others, drive technical reviews, and are committed to sharing your knowledge and standardizing best practices. You are proactive, detail-oriented, and thrive in dynamic environments,



always seeking opportunities to optimize flows, influence architectural decisions, and deliver reliable, high-performance solutions. Your communication skills allow you to convey complex topics clearly to both technical and non-technical audiences, making you a valued partner to circuit, package, board, and product teams.

Drive channel modeling and correlation across time- and frequency-domain analysis: Own and execute SI signoff methodology for SerDes channels, including test chip package/board SIPI model extraction/model quality checks, de-embedding, and ensuring models are bandwidth-appropriate for target data rates. propose design fixes and quantify risk/benefit via simulation and measurement. Define, improve, and document SIPI flows, requirements, and checklists for internal teams and (where applicable) customers; mentor engineers and lead technical reviews.

Provide technical leadership across programs: set priorities, identify cross-project reuse opportunities, and influence architecture choices impacting signal integrity and power integrity. Reduce schedule risk by rapidly diagnosing complex cross-domain issues (silicon/package/board/lab) and guiding practical design changes backed by quantitative analysis. Raise the technical bar by mentoring others, standardizing best practices,



and influencing architectural decisions for next-generation interconnects.

Improve product performance and reliability by ensuring thorough modeling, simulation, and correlation to hardware in diverse environments. Foster a culture of collaboration and continuous improvement within the team and across partnering organizations. D. preferred) in Electrical/Electronic Engineering or related field. ~Robust fundamentals in EM, transmission lines, passive/active modeling, and statistical link analysis; Expertise with high-speed link concepts: insertion/return loss, impedance control, mode conversion, NEXT/FEXT, jitter/noise sources, equalization, BER, etc. ~ Experience with lab correlation and measurement techniques (TDR, VNA, eye/jitter measurements, de-embedding/fixture calibration) and working alongside validation/compliance teams. ~ Proficiency in scripting/automation for flow enablement (Python preferred; Demonstrated technical leadership: mentoring, design reviews, influencing cross-functional decisions, and communicating complex topics clearly to mixed audiences.

Analytical and detail-oriented, with a passion for tackling complex engineering challenges. You will join a global SerDes/PHY design team, and will interact with package and board engineering, validation, and product teams to deliver high-performance interface IP. The team values rigorous analysis, strong correlation to hardware, and practical engineering judgment.

Together, we drive innovation and enable our customers to achieve first-pass success in advanced system environments.

📌 Principal SI/PI Engineer - 18619 (Mississauga)
🏢 Synopsys
📍 Mississauga