24 Oct
|
Schweitzer Engineering Laboratories (SEL)
|
Burnaby
24 Oct
Schweitzer Engineering Laboratories (SEL)
Burnaby
Schweitzer Engineering Laboratories (SEL) in Burnaby, BC is seeking a Lead Engineer focused on VHDL RTL digital logic design to guide our R&D; Communications product group. You will contribute to SONET/VSN multiplexers, Ethernet gateways, and network timing systems while mentoring teammates and shaping architecture.
This role requires hands-on RTL design for FPGAs, strong documentation, and collaboration with product managers to deliver protected, reliable, and economical electric power protection
📌 Lead VHDL RTL FPGA Engineer – Critical Infra (Burnaby)
🏢 Schweitzer Engineering Laboratories (SEL)
📍 Burnaby