2 days ago Be among the first 25 applicantsThis range is provided by Arcadia. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range
CA$150,000.00/yr
- CA$200,000.00/yrLocation: Hybrid – Downtown Toronto (4 days/week in office, near Union Station)Type: Full-time | PermanentCompensation: $150 K–$200 K CAD base + early-stage equityA well-funded AI + semiconductor startup ($30 M+ raised) is hiring a junior/intermediate Design Verification Engineer to help reinvent chip verification through AI-native tooling and intelligent automation.
This is a rare chance to get in early, work alongside senior silicon engineers and ML researchers, and build your career on greenfield verification flows that combine traditional System Verilog/UVM with cutting-edge AI-driven design tools.
What You’ll DoWrite and run System Verilog/UVM testbenches to validate RTL blocks.
Develop directed and constrained-random tests for functional coverage.




Work with senior DV/RTL engineers to define verification plans and metrics.
Automate test execution, regressions, and coverage collection with Python/ntribute to experiments in AI-assisted verification workflows.
What We’re Looking For1–5 years in ASIC/FPGA verification or chip design internships/projects.
Familiarity with System Verilog, UVM, or similar verification methodologies.
Solid scripting skills (Python, TCL, or Shell) for automation.
Solid fundamentals in digital design, RTL, and computer architecture.
Eager to learn and thrive in a fast-paced startup with strong mentorship.
Hands-on coursework or internships with EDA tools (VCS, Questa, Xcelium, etc.).
Exposure to open-source verification frameworks (Coco TB, Verilator).
Knowledge of on-chip protocols (AXI, SPI, PCIe, DDR).
Coursework or curiosity around AI/ML in chip design.

📌 Sr. design verification engineer (Toronto)
🏢 Arcadia
📍 Toronto