We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Analog & Mixed-Signal Modelling Architect – New Grad We are seeking a Analog & Mixed-Signal Modelling Architect – New Grad to join our DSP team. This position emphasizes behavioral modeling using C++ and SystemC, tightly integrated with Python and MATLAB-based system simulations, firmware bring‑up flows, and lab validation. You will operate at the intersection of analog-/digital-hardware, DSP, firmware, and electro‑optical subsystems
- contributing architectural decisions from early concept through silicon bring‑up and product deployment. Develop behavioral models of analog and mixed-signal blocks using C++ and SystemC, emphasizing firmware register‑map interfaces, control, observability, and execution speed. Apply C++/ SystemC-AMS to model continuous‑time and mixed-signal behavior of PLLs, clocking systems, filters, DACs, ADCs, SerDes, and related subsystems. Build and maintain C++ and Python/MATLAB-based verification flows, including C++ MEX wrappers for system simulation environments. Collaborate with analog, digital, DSP, firmware, and lab teams to align models, specifications, and validation plans. Support ASIC lab bring‑up and characterization, correlating silicon and lab data with behavioral models and system simulations. Plan design activities and create design guidelines, implementation documentation, and setup guides in Confluence.

Education:
Post-graduate degree in Physics or Engineering with a focus on ASIC hardware, communication systems, and/or control systems.

Experience:
Previous internship, co-op,



or applied project experience relevant to the role. Experience writing C++ and/or SystemC behavioral models for hardware-adjacent systems. Demonstrated ability to operate at the system-architecture level while remaining grounded in real analog behavior and physical impairments. Knowledge of analog impairments, including noise, distortion, non-linearity, bandwidth limitations, jitter, and phase noise, and their impact on modem-level performance. Strong intuition for analog-digital partitioning, power-performance trade-offs, and calibration strategies. Comfortable working in a Linux-based development environment, using Git and modern collaborative workflows. Clear technical communication skills and the ability to work effectively across disciplines. C++, SystemC-AMS, Python, MATLAB, Simulink, Cadence Virtuoso, Cadence AMS Designer, Xcelium AMS. The annual salary range for a Masters Recent Grad is $70,700
- $112,900. The annual salary range for PhD New Grads is $89,000
- $142,200. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

📌 Analog and Mixed-Signal Modelling Architect (Canada)
🏢 Ciena
📍 Canada