Job Title Lead Verification Engineer
Locations Montreal, Ottawa, Toronto
Overview At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This role is for an existing vacancy. This is an prospect to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks within required project timelines with high quality. The candidate will primarily be responsible for the verification of digital RTL and development of re‑usable verification components and environments. It is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure. The ideal candidate will have a fundamental understanding of the end‑to‑end verification flow in order to accurately and efficiently communicate with all members of the technical staff regarding overall project development progress and status. The most successful candidates will be able to demonstrate excellent command of fundamental logic principles as well as excellent problem solving and communication skills. The candidate should be able to work as part of a small and focused team of engineers and be able to collaborate successfully as needed with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies. The candidate should be willing to work full time in the Montreal, Quebec, Canada office and be willing to travel as required by job function (expectation is 5% travel or less).



Design IP is a growing organization within Cadence and our complete IP portfolio can be found here Responsibilities Verify digital RTL and develop reusable verification components and environments.
Contribute to all aspects of digital verification, including flow development, test plan development and execution, functional coverage closure, and code coverage closure.
Communicate with all technical staff regarding project development progress and status.
Collaborate with design teams, verification teams, project management, and digital and analog design teams across multiple worldwide geographies.
Work independently to complete assigned tasks within required project timelines with high quality.
Minimum Experience Bachelor of Science in Electrical (EE)/Computer Engineering (CPE) or Computer Science (CSC)
Understanding of verification architecture and methodologies
Understanding of Metric Driven Verification
Understanding of Universal Verification Methodologies
Understanding of the identification, planning and creation of functional coverage and checks
Understanding of System Verilog Assertions (SVAs)
Understanding of digital design flow
Preferred Experience Master of Science in EE/CPE/CSC
Experience with System Verilog UVM coding language
Experience with scripting languages such as Python, Perl, Ruby, Sed, or Awk
Exposure to Standard Protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI




Exposure to Formal Verification Technologies
Exposure to Mixed Signal Design experience
Experience with Cadence tools
Exposure to Low Power verification experience using CPF or UPF
Equal Opportunity Employer Cadence is an equal-opportunity employer committed to hiring a diverse workforce.
Titre: Concepteur en Vérification Numérique Localisation: Montreal, Ottawa, Toronto
Description (Fr) Cadence Design Systems est à la recherche de candidats d’excellence pour joindre une équipe expérimentée et dynamique d’ingénieurs en charge du développement d’IP au service des standards de l’industrie. Le candidat sélectionné aura la charge de la vérification de modules numériques RTL et du développement de modules de vérification réutilisables. Le candidat sera aussi amené à contribuer à toutes les phases du processus de vérification : élaboration du plan de vérification, codage des points de couverture, génération de stimuli et analyse de couverture. Le candidat devra posséder des connaissances de base des méthodes de design et de vérification des composantes numériques. Le candidat devra être autonome, dynamique et démontrer de très bonnes qualités de communication. Le groupe de design IP est une équipe multidisciplinaire composée d’ingénieurs provenant de divers sites à travers le monde. Faisant parti du groupe de vérification, le candidat sera amené à collaborer avec diverses disciplines et phases de la réalisation complète d’IP matériel : design numérique et analogique, design physique, production, etc. Le groupe de design IP est une organisation grandissante. Le catalogue complet se trouve au site suivant : Expérience minimum (Fr) Baccalauréat en Ingénierie électriq

📌 Lead digital verification engineer (Montreal)
🏢 Cadence Design Systems
📍 Montreal