Design AMD PCIe solutions through RTL implementation and front-to-back flows, contributing to power-productive, performance-optimized ASIC development. As an ASIC Design Engineer focused on PCIe IP Enablement, you will support architecture, IP design, RTL implementation, and SoC deployment. The work requires digital design expertise, Verilog HDL, and end-to-end ownership of complex digital IP or subsystems. You will collaborate across IP design, Physical Design, and SoC teams. Key Responsibilities:
Integrate AMD PCI Express subsystems and deploy IP to SoCs Complete synthesis, timing, lint, and CDC closure Implement test, debug, and clock-related design elements Apply UPF-based power-aware design flows and checks Develop automation, scripting, and design flows hands-on Requirements:
ASIC hardware design experience with end-to-end ownership Strong digital RTL design and Verilog HDL knowledge Experience with synthesis, lint, CDC, equivalence, and STA Knowledge of low-power techniques and UPF or CPF flows Bachelor's or Master's degree in Electrical or Computer Engineering preferred Bring PCIe integration, RTL quality, power-aware design, and technical problem-solving expertise to AMD ASIC development.